1. Field of the Invention
The present invention relates generally to CMOS (complementary metal oxide semiconductor) image sensors, and more particularly, to offset correction of a comparator using current control during correlated double sampling for reduced area of the CMOS image sensor.
2. Background of the Invention
CMOS image sensors are recently in wide use with increase of demand for portable cameras. As is well known, CMOS image sensors have higher degree of integration and consume less power than a charge coupled device (CCD). Thus, CMOS image sensors are increasingly used in mobile phones, light digital cameras, etc.
FIG. 1 is a schematic diagram of a conventional CMOS image sensor. Referring to FIG. 1, the conventional CMOS image sensor includes a pixel array 10 having a matrix of a plurality of pixels with each pixel including a single photo diode and four transistors, a row decoder 11 driving rows of the pixel array 10, a CDS (correlated doubling sampling)/analog-to-digital conversion (ADC) unit 12 for columns of the pixel array 10, and a memory unit 13 for storing digitized pixel signals.
The CMOS image sensor of FIG. 1 sequentially outputs rows of image signals from the pixel array 10. Meanwhile, to reduce reset noise and fixed pattern noise occurring in each pixel, CDS is performed by the CDS/ADC unit 12 that also performs ADC.
FIG. 2 illustrates a first conventional CDS/ADC unit. Referring to FIG. 2, the first conventional CDS/ADC unit includes switches 20a and 20b for selectively coupling signals from a pixel to inputs of a comparator 22. In addition, the first conventional CDS/ADC unit includes a first capacitor 21b for storing a reset voltage switched by a switch 20b from the pixel during a reset sampling period, and includes a second capacitor 21a for storing a sensing voltage switched by a switch 20a from the pixel during a signal sampling period.
The comparator 22 has a negative input coupled to one end of the first capacitor 21b and the first switch 20b and has a positive input coupled to one end of the second capacitor 21 and the second switch 20a. A decreasing ramp voltage RAMP− is applied to the other end of the first capacitor 21b, and an increasing ramp voltage RAMP+ is applied to the other end of the second capacitor 21a. 
With such ramp voltages applied, the comparator 22 generates an output that makes a logical transition at a time point that is dependent on a difference between the reset voltage and the sensing voltage from the pixel. A memory/latch unit 23 stores a gray code that has been sequentially changing with time at such a time point. The stored gray code is the digital value representing the difference between the reset voltage and the sensing voltage from the pixel. Such a difference between the reset voltage and the sensing voltage represents the intensity of light received at the photo-diode without a pixel offset.
A respective conventional CDS/ADC of FIG. 2 is used for each column of the pixel array. However, a respective offset for each comparator 22 of the columns may be different between the columns resulting in inaccurate and non-uniform CDS and ADC across the columns.
FIG. 3 illustrates a second conventional CDS/ADC unit that compensates for comparator offset. Referring to FIG. 3, the second conventional CDS/ADC unit includes switches 30a and 30b for selectively coupling signals from a pixel to inputs of a comparator 32. In addition, the second conventional CDS/ADC unit includes a first capacitor 31b for storing a reset voltage transferred from the pixel through a switch 30b and includes a second capacitor 31a for storing a sensing voltage transferred from the pixel through a switch 30a. 
The first comparator 32 has a positive input coupled to the second capacitor 31a and the switch 30a and has a negative input coupled to the first capacitor 31b and the switch 30b. The outputs from the first comparator 32 are coupled to inputs of a second comparator 35 via third and fourth capacitors 33a and 33b that correct an offset of the first comparator 32.
Switches 34a and 34b apply an intermediate voltage (e.g., VDD/2) on the third and fourth capacitors 33a and 33b, respectively, when turned on. The second comparator 35 performs offset-corrected CDS. A memory/latch unit 36 stores a gray code at a time point when the output of the second comparator 35 makes a logical transition while the ramp voltages RAMP+ and RAMP− are applied after the reset signal and the sensing signal are applied on the capacitors 31b and 31a. 
The second conventional CDS/ADC unit uses the additional capacitors 33a and 33b to store the offset of the first comparator 32. To correct for such an offset, the switches 30a and 30b are simultaneously closed when the reset signal is applied to both inputs of the first comparator 32. In this situation, the first comparator 32 has a positive output voltage and a negative output voltage at its two outputs from its own offset. To correct such an offset, the switch 34a is closed such that the offset of the first comparator 32 is stored in the fourth capacitor 33b. 
Unfortunately, an amplification gain of the first comparator 32 cannot be increased in the second conventional CDS/ADC unit of FIG. 3. In detail, when an amplification gain is large, an output of the first comparator 32 is easily saturated even through a difference between inputs of the first comparator 32 is small, and even a small offset cannot be corrected.
When a voltage gain increases, the operating speed of the first comparator 32 is reduced. However, the influence of an offset of the second comparator 35 is reduced as much as the voltage gain of the first comparator 32. Thus, a small gain of the first comparator 32 is disadvantageous.
To overcome this problem, the first comparator 32 having a small voltage gain is used and then an offset correction circuit, which is provided after the first comparator 32 as described above, may be implemented again after the second comparator 35. However, in this case, circuit area and manufacturing price are disadvantageously increased with higher number of components.